// Copyright 2018 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

#pragma once

typedef enum g12a_clk_gate_idx {
  // SYS CPU CLK
  CLK_SYS_PLL_DIV16 = 0,
  CLK_SYS_CPU_CLK_DIV16,

  CLK_DDR,
  CLK_DOS,
  CLK_ALOCKER,
  CLK_MIPI_DSI_HOST,
  CLK_ETH_PHY,
  CLK_ISA,
  CLK_PL301,
  CLK_PERIPHS,
  CLK_SPICC_0,
  CLK_I2C,
  CLK_SANA,
  CLK_SD,
  CLK_RNG0,
  CLK_UART0,
  CLK_SPICC_1,
  CLK_HIU_REG,
  CLK_MIPI_DSI_PHY,
  CLK_ASSIST_MISC,
  CLK_EMMC_A,
  CLK_EMMC_B,
  CLK_EMMC_C,
  CLK_ACODEC,
  CLK_AUDIO,
  CLK_ETH_CORE,
  CLK_DEMUX,
  CLK_AIFIFO,
  CLK_ADC,
  CLK_UART1,
  CLK_G2D,
  CLK_RESET,
  CLK_PCIE_COMB,
  CLK_PARSER,
  CLK_USB_GENERAL,
  CLK_PCIE_PHY,
  CLK_AHB_ARB0,
  CLK_AHB_DATA_BUS,
  CLK_AHB_CTRL_BUS,
  CLK_HTX_HDCP22,
  CLK_HTX_PCLK,
  CLK_BT656,
  CLK_USB1_TO_DDR,
  CLK_MMC_PCLK,
  CLK_UART2,
  CLK_VPU_INTR,
  CLK_GIC,
  CLK_VCLK2_VENCI0,
  CLK_VCLK2_VENCI1,
  CLK_VCLK2_VENCP0,
  CLK_VCLK2_VENCP1,
  CLK_VCLK2_VENCT0,
  CLK_VCLK2_VENCT1,
  CLK_VCLK2_OTHER,
  CLK_VCLK2_ENCI,
  CLK_VCLK2_ENCP,
  CLK_DAC_CLK,
  CLK_AOCLK_GATE,
  CLK_IEC958_GATE,
  CLK_ENC480P,
  CLK_RNG1,
  CLK_VCLK2_ENCT,
  CLK_VCLK2_ENCL,
  CLK_VCLK2_VENCLMMC,
  CLK_VCLK2_VENCL,
  CLK_VCLK2_OTHER1,

  // NB: This must be the last entry
  CLK_G12A_COUNT,
} g12a_clk_gate_idx_t;
